2 retiming logic, Retiming logic – Avago Technologies LSI53C140 User Manual

Page 22

2-4

Functional Descriptions

Ver. 2.1

2.1.1.3 LVDlink Technology

To support greater device connectivity and longer SCSI cables, the
LSI53C140 features LVDlink technology, the LSI Logic implementation of
multimode LVD SCSI. LVDlink transceivers provide the inherent reliability
of differential SCSI, and a long-term migration path of faster SCSI
transfer rates.

LVDlink technology is based on current drive. Its low output current
reduces the power needed to drive the SCSI bus. Therefore, the I/O
drivers can be integrated directly onto the chip. This reduces the cost and
complexity compared to traditional (high power) differential designs.
LVDlink lowers the amplitude of noise reflections and allows higher
transmission frequencies.

The LVDlink transceivers in side A and side B operate in the LVD, HVD
(external differential transceivers), or SE modes. The LSI53C140
automatically detects the type of signal connected, based on the voltages
detected by A_DIFFSENS and B_DIFFSENS.

2.1.2 Retiming Logic

As SCSI signals propagate from one side of the LSI53C140 to the other
side, the logic circuits that retime the bus signals process the SCSI
signals, as needed. This guarantees or improves the required SCSI
timings. The State Machine Controls govern the retiming logic that keeps
track of SCSI phases, the location of initiator and target devices, and
various timing functions. In addition, the retiming logic contains
numerous delay elements that are periodically calibrated by the Precision
Delay Control block. This calibration occurs in order to guarantee
specified timing such as output pulse widths, setup and hold times, and
others.

When a synchronous negotiation takes place between devices, a nexus
is formed, and the on-chip RAM stores the corresponding information for
that nexus. This information remains in place until a chip reset, power
down, or renegotiation occurs. This enables the chips to make more
accurate retiming adjustments.