Avago Technologies LSI53C140 - Manual (Page 52)

3-18 LSI53C140 Specifications
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
I
LL
Input low leakage – –20
µ
A V
DD
±
5%
,
V
PIN
= 0 V
I
PD
Power down leakage – 20
µ
A V
DD
= 0 V,
V
PIN
= 1.2 V
R
I
Input resistance 20 – M
Ω
SCSI pins
4
C
P
Capacitance per pin – 15 pF PQFP
t
R
2
Rise time, 10% to 90% 4.0 18.5 ns Figure 3.7
t
F
Fall time, 90% to 10% 4.0 18.5 ns Figure 3.7
dV
H
/dt Slew rate, LOW to HIGH 0.15 0.50 V/ns Figure 3.7
dV
L
/dt Slew rate, HIGH to LOW 0.15 0.50 V/ns Figure 3.7
ESD Electrostatic discharge 2 – kV MIL-STD-883C;
3015-7
Latch-up 100 – mA –
Filter delay 20 30 ns Figure 3.8
Ultra filter delay 10 15 ns Figure 3.8
Ultra2 filter delay 5 8 ns Figure 3.8
Extended filter delay 40 60 ns Figure 3.8
1. These values are guaranteed by periodic characterization; they are not 100% tested on every device.
2. Active negation outputs only: Data, Parity, SREQ/, SACK/. (Minus Pins) SCSI mode only.
3. Single pin only; irreversible damage may occur if sustained for more than one second.
4. SCSI RESET/ pin has 10 k
Ω
pull-up resistor.
Table 3.15 TolerANT Technology Electrical Characteristics
1
(Cont.)
Symbol Parameter Min Max Units Test Conditions
(Sheet 2 of 2)