Avago Technologies LSI53C140 - Manual (Page 26)

2-8 Functional Descriptions
Ver. 2.1 Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
1. The receiver logic accepts the asserted data as soon as it is
received. Once the clock signal has been received, data is gated
from the receiver latch.
2. The path is next tested to ensure the signal, if being driven by the
LSI53C140, is not misinterpreted as an incoming signal.
3. The data is then leading edge filtered. The assertion edge is held for
a specified time to prevent any signal bounce. The input signal
controls the duration.
4. The next stage uses a latch to sample the signal. This provides a
stable data window for the load bus.
5. The final step develops pull-up and pull-down controls for the SCSI
I/O logic, including 3-state controls for the pull-up.
6. A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
2.2.2 SCSI Bus Activity LED (BSY_LED)
Internal logic detects SCSI bus activity and generates a signal that
produces an active HIGH output. This output can be used to drive a LED
to indicate SCSI activity.
The internal circuitry is a digital one shot that is active HIGH with a
minimum pulse width of 16 ms. The BSY_LED output current is 8 mA.
This output may have an LED attached to it with the other lead of the
LED grounded through a suitable resistor.
2.2.3 Select Control (SSEL)
A_SSEL and B_SSEL are control signals used during bus arbitration and
selection. Whichever side asserts, SSEL propagates it to the other side.
If both signals are asserted at the same time, the A Side receives SSEL
and sends it to the B Side. This output has pull-down control for an open
collector driver. The select control signals go through this process: