Sundance SMT390-VP - Manual (Page 5)

Version 2.4 Page 5 of 55 SMT390-VP User Manual
Green LEDs ............................................................................................................ 23
ADC Data Interface................................................................................................. 23
Clock synthesizer Interface..................................................................................... 23
Clock Routing.......................................................................................................... 23
TIM Interface ........................................................................................................... 23
RSL Interface (RSL are not available) .................................................................... 23
RSL Connector and Pinout Definition ................................................................. 23
RSL Cable Definition ........................................................................................... 27
SHB......................................................................................................................... 27
Daughter-card Interface .......................................................................................... 30
Firmware description .................................................................................................. 37
SHB full word configuration..................................................................................... 38
SHB half word configuration ................................................................................... 38
Setting-up an acquisition ............................................................................................ 38
Configuring the FPGA ................................................................................................ 39
Control Register Settings............................................................................................ 40
Control Packet Structure......................................................................................... 40
Reading and Writing Registers ............................................................................... 40
Memory Map ........................................................................................................... 41
Register Descriptions.............................................................................................. 42
Global FPGA Reset Register (0x00) ................................................................... 42
Clock Synthesizer Control Register (0x02) ......................................................... 42
Clock Routing Selection Register (0x03) ............................................................ 42
Acquisition trigger register (0x06) ....................................................................... 43
ADC Setup Control Register (0x07) .................................................................... 44
Decimation Register (0x08)................................................................................. 44
SHB Control Register (0x09)............................................................................... 44
Main Module Temperature Register (0x0A)........................................................ 45
Main Module FPGA Temperature Register (0x0B) not available........................ 45
Daughter Module Temperature Register (0x0C) not available ........................... 45
Daughter Module ADC Temperature Register (0x0D) not available .................. 45
Main Module Silicon Serial Number Words0, 1, 2 and 4 (0x10, 11, 12 and 13). 45
Daughter Module Silicon Serial Number Words0, 1, 2 and 4 (0x14, 15, 16 and
17). not available ................................................................................................. 45