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Bank a bank b bank c, Bank b – Sundance SMT390-VP User Manual

Page 34

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Version 2.4

Page 34 of 55

SMT390-VP User Manual

Bank

A Bank

B Bank

C

1 3 5 7

41 43

81 83



2 4 6 8

Bank B

Pin No

Pin Name

Signal Description

Pin No

Pin Name

Signal Description

Type

Clock and Trigger System Signals

Type

Clock and Trigger System Signals

Dir

Daughter Card to Main Module

Dir

Daughter Card to Main Module

41

SMBClk

Temperature Sensor Clock.

42

SMBData

Temperature Sensor Data.

43

SMBnAlert

Temperature Sensor Alert.

44

SerialNo

Serial Number Data Line.

Dir

Daughter Card to Main Module

Dir

Reserved

45 AdcVDacI

Reserved

46 AdcVDacQ

Reserved

47 AdcVRes

Reserved

48 AdcReset Reserved

Dir

Main Module to Daughter Card

Dir

Main Module to Daughter Card

49

D3v3Enable

3.3V Power Enable

50

D2v5Enable

5V Power Enable

51

AdcMode

Data Format (2’s/bin), ChA.

52

AdcClock

Half or Full Scale, ChA.

Type

ADC Specific Signals

Type ADC

Specific

Signals

Dir

Main Module to Daughter Card

Dir

Reserved

53

AdcLoad

Data Format (2’s/bin), ChB.

54

AdcData

Half or Full Scale, ChB.

55

AdcCal

Reserved.

56

AdjClkCntr0

Adj. Clock Serial Clock.

Dir

Main Module to Daughter Card

Dir

Main Module to Daughter Card

57

AdjClkCntr1

Adj. Clock Serial Data.

58

AdjClkCntr2

Adj. Clock Serial Load.

59

AdjClkCntr3

Adj. Clock Serial Test.

60

PllCntr0

Led1

Dir

Daughter Card to Main Module

Dir

Daughter Card to Main Module

61 PllCntr1

Led2

62 PllCntr2 Led3

63

PllCntr3

Led4

64

AdcAClkSel

Clock Selection, ChA

Type

Module Control Signals

Type

Module Control Signals

Dir

Main Module to Daughter Card

Dir

Main Module to Daughter Card

65

AdcBClkSel

Clock Selection, ChB

66

IntClkDivEn

AdcAClkOpp

67 IntClkDivnReset

Reserved.

68 IntExtClkDivEn

AdcBClkOpp

Dir

Main Module to Daughter Card

Dir

Main Module to Daughter Card

69 IntExtClkDivnReset

Reserved.

70 FpgaVRef JTAG

FPGA

Vref.

71

FpgaTck

JTAG FPGA tck.

72

FpgaTms

JTAG FPGA tms.

Dir

Daughter Card to Main Module

Dir

Reserved

73

FpgaTdi

JTAG FPGA tdi.

74

FpgaTdo

JTAG FPGA tdo.

75

MspVRef

JTAG MSP430 Vref

76

MspTck

JTAG MSP430 tck.

Dir

Daughter Card to Main Module

Dir

Reserved

77

MspTms

JTAG MSP430 tms.

78

MspTdi

JTAG MSP430 tdi.