Sundance SMT390-VP - Manual (Page 18)

Version 2.4 Page 18 of 55 SMT390-VP User Manual
SHB Interface
The retrieved data from the ‘Retrieve from Memory’ block is transmitted over the SHB
interface. The SHB interface controls the SHB bus between the SMT390-VP and any
module connected to the SHB requesting the data.
Clock Structure
There is an integrated clock generator on the module. The user can either use this
clock or provide the module with an external clock (input via MMCX connector). The
RSL interface will only function if the module’s integrated clock is used (RSL are not
available).
External Clocks Module Clock
FPGA
Clock synthsizer
Clock
Control
TTL to LVPECL
LVPECL
Buffers
External Clock Inputs
(MMCX)
4:2 Mux with Dual Output
ADCA
Ch
A
C
lo
ck
Ch
B
C
lo
ck
LVDS
SerDes
Clock
Sys
Clock
DLL
RSL
Clock
DLL
Diagram Key:
210 MHz LVPECL Clock
ADCB
Figure 7 - Clock Structure.