Sundance SMT390-VP - Manual (Page 19)

Version 2.4 Page 19 of 55 SMT390-VP User Manual
Each ADC can receive as encode signals, the on-board clock or its own external
clock or the other channel’s clock. It also means that an external clock can encode
both ADCs.
Power Supply and Reset Structure
The SMT390-VP conforms to the TIM standard for single width modules. The TIM
connectors supply the module with 5.0V. The module also requires an additional
3.3V power supply, which must be provided by the two diagonally opposite mounting
holes. This 3.3V is present on all Sundance TIM carrier boards. From the 5.0V the
FPGA Core Voltage (V
CCINT
= 1.5V), the FPGA Auxiliary voltage (V
CCAUX
= 2.5V) is
generated. The FPGA IO Voltage (V
CCO
= 3.3V) is taken straight from the TIM
mounting holes. The 3.3V, 5.0V, +12V and –12V present on the TIM connector are
passed up to the daughter card, as well as a 1.5V and a 2.5V. The daughter card is
responsible for generating its required voltages.
A TI MSP430 low power microprocessor is located on the main module. This
microprocessor controls the power sequencing for the main module. High efficiency
Vishay DC/DC converters are used to generated the lower voltages.
On the daughter card the Analog Devices ADCs require analog and digital 3.3V. The
3.3V from the main module to daughter card power connector is used for the digital
3.3V. This voltage is taken from the 5-Volt rail and filtered to provide the analog 3.3V.
The MSP430 microprocessor also controls the reset sequence for the SMT390-VP.
There are two possible reset sources for the SMT390-VP:
1. A reset is received over the TIM connector
2. After power up an internal Power On Reset in the MSP430 causes a reset