Sundance SMT390-VP - Manual (Page 37)

Version 2.4 Page 37 of 55 SMT390-VP User Manual
Firmware description
At reset, FPGA is in the INIT state where internal memory and registers are reset.
It then waits for an acquisition trigger command to happen to start storing data into
internal memory (state “STORE”).
Once memory is full, data start to be read back (state “READ BACK”).
When the whole memory has been read back FPGA goes back into “WAIT START
CMD” state and wait for a new acquisition trigger command to happen.
The following diagram describes the sequence of events during an acquisition:
Wait start
cmd
Read back
Store
TIM Reset or ComPort
Reset
Memory empty
INIT
Memory full
Acquisition triggered
Figure 20: SMT390-VP state diagram