Sundance SMT390-VP - Manual (Page 13)

Version 2.4 Page 13 of 55 SMT390-VP User Manual
Analog data enters the module via two MMCX connectors, one for each channel.
Both signals are then conditioned (AC coupling) before being digitized. Both ADCs
gets their own sampling clock, which can be either on-board generated or from an
external source (MMCX connector). ADCs can receive either their own external clock
or both the same external clock or both the same on-board clock, or even opposite
external clocks. Two more MMCX connectors are dedicated for two external trigger
signals. External clocks and triggers can be either single-ended or differential (the
selection is made on hardware), whereas the analogue input is single-ended only.
ADCs digital outputs are fed into the FPGA. They can be passed directly on both
SHB connectors or stored into the on-board DDR SDRAM memory to be transferred
afterwards via SHB connectors. ADCs data stream can also be transmitted via RSL
connectors (RSL will be available on a future version of the FPGA firmware).
The design of the SMT390-VP is split over two PCBs. The main PCB (main module –
SMT338-VP
) contains the FPGA, the memory, the microcontroller and the digital
connector interfaces (TIM, SHB and RSL). The second PCB (daughter card –
SMT390
) contains all the analogue circuitry as well as the clock generation, trigger
control, analogue signal conditioning and ADCs.
The FPGA gets control words from a ComPort interface following the Texas
Instrument
C4x standard . It then feeds both ADCs with a differential encode signal,
from one of the following sources: external (via MMCX connector) or internal (on-
board clock generator). Two parallel LVDS buses carry 12-bit samples (2’s
complement or offset binary format -
SLB ) from both converters to the FPGA, which
sends them out through both SHB connectors. Note that samples coming from ADC
Channel A are output on SHBB (J8) and that samples coming from ADC Channel B
are output on SHBA (J7).
Two full (60-pin) SHB connectors are accessible from the FPGA. They are output
only to send out digital samples to another module. Please refer to
the SHB
specifications for more details about ways connectors can be configured.
A global reset signal is mapped to the FPGA from the bottom TIM connector via the
MSP430 microcontroller.
Communication Ports (ComPorts).
The SMT390-VP provides 2 ComPorts: 0 and 3.
ComPort 3 is used to configure and send control words the FPGA.
The
SMT6400 help file provides more information about ComPorts.
The ComPorts drive at 3.3v signal levels.
Sundance High-speed Bus - SHB.
2 SHB connectors are used to transmit data coming from ADCs to external world.
Both
SHB
buses are identical and 60-bit wide.
See SHB technical specification for more information.