Altera Nios Development Board - Manual (Page 51)

Altera Corporation Index–1
Nios Development Board Reference Manual, Stratix Edition
Index
A
Appendix A
Shared bus table A–1
Appendix C
Board Ethernet connection C–1
B
Block diagram 1–3
Board Ethernet connection
Browse the board C–5
Connecting the Ethernet cable C–1
Connecting the LCD display C–2
Obtaining an IP Address C–2
C
Clock circuitry 1–27
CompactFlash connector 1–5
Configuration and reset buttons 1–25
SW10 - Reset config 1–26
SW8 - CPU reset 1–25
SW9 - Safe config 1–26
Configuration controller device 1–21
Configuration data 1–21
Configuration-status LEDs 1–24
indicators 1–25
Reset distribution 1–21
Safe and user configurations 1–22
Starting configuration 1–21
Stratix configuration 1–21
Conventional flash memory usage 1–22
D
Development board
Component illustration 1–3
Features 1–1
General description 1–1
Dual 7-segment display 1–19
U8 & U9 pin information 1–19
E
Ethernet MAC/PHY 1–11
Expansion prototype connector
(PROTO1) 1–11
J11 pin information 1–13
J12 pin information 1–13
J13 pin information 1–14
Expansion prototype connector
(PROTO2) 1–14
J15 pin information 1–15
J16 pin information 1–15
J17 pin information 1–16
F
Flash memory allocation 1–23
Flash memory device 1–4
I
Individual LEDs (D0 - D7) 1–20
pin information 1–20
J
JTAG connectors 1–28
JTAG connector to MAX device (J5) 1–29
JTAG to Stratix device (J24) 1–28
M
Mictor connector 1–16
J25 pin information 1–18
P
Power-supply circuitry 1–26
Push-button switches 1–20