Altera Nios Development Board - Manual (Page 39)

Altera Corporation A–1
September 2004
Appendix A. Shared Bus Table
Description On the Nios development board, Stratix Edition, the flash memory,
SRAM and Ethernet MAC/PHY devices share address and control lines.
These shared lines are referred to as the Shared Bus. Using SOPC Builder,
designers can interface a Nios II processor system to any device
connected to the off-chip Shared Bus.
Table A–9 on page A–1 lists all
connections between the devices connected to the Shared Bus.
Table A–9. Shared Bus Table (Part 1 of 3)
NET Name
NET
Description
PLD (U53) Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4)
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin
#
Pin
Name
Pin #
Pin
Name
Pin #
FSE_A0 Shared
Address IO A4 A0 27
FSE_A1 IO A3 A1 22 A1 78
FSE_A2 IO B3 A2 21 A0 1 A0 1 A2 79
FSE_A3 IO B5 A3 20 A1 2 A1 2 A3 80
FSE_A4 IO B4 A4 19 A2 3 A2 3 A4 81
FSE_A5 IO C4 A5 18 A3 4 A3 4 A5 82
FSE_A6 IO A5 A6 17 A4 5 A4 5 A6 83
FSE_A7 IO C5 A7 16 A5 18 A5 18 A7 84
FSE_A8 IO D5 A8 10 A6 19 A6 19 A8 85
FSE_A9 IO E6 A9 9 A7 20 A7 20 A9 86
FSE_A10 IO A6 A10 42 A8 21 A8 21 A10 87
FSE_A11 IO B7 A11 8 A9 22 A9 22 A11 88
FSE_A12 IO D6 A12 7 A10 23 A10 23 A12 89
FSE_A13 IO A7 A13 6 A11 24 A11 24 A13 90
FSE_A14 IO D7 A14 5 A12 25 A12 25 A14 91
FSE_A15 IO C6 A15 4 A13 26 A13 26 A15 92
FSE_A16 IO C7 A16 3 A14 27 A14 27
FSE_A17 IO B6 A17 46 A15 42 A15 42
FSE_A18 IO D8 A18 15 A16 43 A16 43
FSE_A19 IO C8 A19 43 A17 44 A17 44
FSE_A20 IO E8 A20 44
FSE_A21 IO D9 A21 35
FSE_A22 IO B9 A22 2