Altera Nios Development Board - Manual (Page 16)

1–8 Altera Corporation
Nios Development Board Reference Manual, Stratix Edition September 2004
SDRAM Device
f
For more information on the CompactFlash connector (CON3), see
www.compactflash.org
and www.molex.com.
SDRAM Device The SDRAM device (U57) is a Micron MT48LC4M32B2 with PC100
functionality and self refresh mode. The SDRAM is fully synchronous
with all signals registered on the positive edge of the system clock.
34 -OIORD M9
35 -IOWR M10
36 -WE L5
37 RDY/BSY M5
38 VCC H4 (2)
39 -CSEL GND (3)
40 -VS2 no connect (3)
41 RESET (4)
42 -WAIT K1
43 -INPACK J4
44 -REG G2
45 BVD2 J1
46 BVD1 M8
47 D081 N10
48 D091 M2
49 D101 N5
50 GND GND (3)
Note to Table 1–1
(1) All pin numbers represent I/O pins on the FPGA, unless otherwise noted.
(2) This FPGA I/O pin controls a power MOSFET that supplies 5V VCC to CON3.
(3) This pin does not connect to the FPGA directly.
(4) RESET is driven by the EPM7128AE configuration controller device.
Table 1–2. CompactFlash (CON3) Pin Table
Pins on CompactFlash
(CON3)
CompactFlash Function Connects To (1)