Altera Nios Development Board User Manual
Page 14
1–6
Altera
Corporation
Nios Development Board Reference Manual, Stratix Edition
September 2004
CompactFlash Connector
■
Pin 13 of CON3 (VCC) is driven by a power MOSFET that is
controlled by an FPGA I/O pin. This allows the FPGA to control
power to the CompactFlash card for the IDE connection mode.
■
Pin 26 of CON3 (-CD1) is pulled up to 5V through a 10 Kohm resistor.
This signal is used to detect the presence of a CompactFlash card;
when the card is not present, the signal is pulled high through the
pull-up resistor.
■
Pin 41 of CON3 (RESET) is pulled up to 5V through a 10 Kohm
resistor, and is controlled by the EPM7128AE configuration
controller. The FPGA can cause the configuration controller to assert
RESET, but the FPGA does not drive this signal directly.
1
The CompactFlash connector shares several Stratix I/O pins
with expansion prototype connector PROTO1. See 2
Prototype Connector (PROTO1)” on page 1–11
for details on
PROTO1.
below provides CompactFlash pin out details.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)