Altera Nios Development Board - Manual (Page 22)

1–14 Altera Corporation
Nios Development Board Reference Manual, Stratix Edition September 2004
Expansion Prototype Connector (PROTO2)
Figure 1–7. Expansion Prototype Connector - J13
Note to Figure 1–7
(1) Unregulated voltage from AC to DC power transformer
(2) Clk from board oscillator
(3) Clk from FPGA via buffer
(4) Clk output from protocard to FPGA
Expansion
Prototype
Connector
(PROTO2) Headers JP15, JP16, and JP17 collectively form the standard-footprint,
mechanically-stable connection that can be used (for example) as an
interface to a special-function daughter card.
The expansion prototype connector interface includes:
■ 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins
on the Stratix device. Each signal passes through analog switches
(U27, U28, U29, U30 and U31) to protect the Stratix device from 5-V
logic levels. These analog switches are permanently enabled.
■ A buffered, zero-skew copy of the on-board OSC output (from U2).
■ A buffered, zero-skew copy of the Stratix's phase-locked loop (PLL)-
output (from U53).
■ A logic-negative, power-on reset signal.
■ Five regulated 3.3-V power-supply pins (2A total max load for both
PROTO1 & PROTO2).
■ One regulated 5-V power-supply pin (1A total max load for both
PROTO1 & PROTO2).
■ Numerous ground connections.
The output logic-level on the expansion prototype connector pins is 3.3V.
The power supply included with the Nios II development kit cannot
supply the maximum load current specified above.