Altera FFT MegaCore Function User Manual
Page 8
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Device
Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Type
Length
Engines
M10K M20K Primar
y
Secondar
y
Arria
V
Burst
Quad
Output
256
2
2,474
12
14
--
5,768
233
27
5
Arria
V
Burst
Quad
Output
256
4
4,403
24
27
--
10,443 437
25
7
Arria
V
Burst
Quad
Output
4,096
1
1,597
6
27
--
3,949
151
27
5
Arria
V
Burst
Quad
Output
4,096
2
2,551
12
27
--
6,119
223
27
5
Arria
V
Burst
Quad
Output
4,096
4
4,494
24
27
--
10,844 392
25
6
Arria
V
Burst
Single
Output
1,024
1
672
2
6
--
1,488
101
27
5
Arria
V
Burst
Single
Output
1,024
2
994
4
10
--
2,433
182
27
5
Arria
V
Burst
Single
Output
256
1
636
2
3
--
1,442
95
27
5
Arria
V
Burst
Single
Output
256
2
969
4
8
--
2,375
152
27
5
Arria
V
Burst
Single
Output
4,096
1
702
2
19
--
1,522
126
27
0
Arria
V
Burst
Single
Output
4,096
2
1,001
4
25
--
2,521
156
27
5
Arria
V
Streaming 1,024
—
1,880
6
20
--
4,565
167
27
5
Arria
V
Streaming 256
—
1,647
6
20
--
3,838
137
27
5
Arria
V
Streaming 4,096
—
1,819
6
71
--
4,655
137
27
5
UG-FFT
2014.12.15
Performance and Resource Utilization
1-5
About This IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
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- ALTDQ_DQS2 (100 pages)
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- Cyclone V Avalon-MM (166 pages)
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- Stratix V Avalon-ST (293 pages)
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- Arria 10 Avalon-ST (275 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
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- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)