Altera FFT MegaCore Function User Manual
Page 11
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Device
Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Type
Length
Engines
M10K M20K Primar
y
Secondar
y
Cycl
one
V
Burst
Single
Output
4,096
1
695
2
19
--
1,540
105
23
7
Cycl
one
V
Burst
Single
Output
4,096
2
1,009
4
25
--
2,536
116
24
0
Cycl
one
V
Streaming 1,024
—
1,869
6
20
--
4,573
132
21
1
Cycl
one
V
Streaming 256
—
1,651
6
20
--
3,878
85
22
6
Cycl
one
V
Streaming 4,096
—
1,822
6
71
--
4,673
124
19
9
Cycl
one
V
Variable
Streaming
Floating
Point
1,024
—
11,184 48
89
--
18,830 628
13
3
Cycl
one
V
Variable
Streaming
Floating
Point
256
—
8,611
36
62
--
15,156 467
13
3
Cycl
one
V
Variable
Streaming
Floating
Point
4,096
—
13,945 60
138
--
22,615 701
13
2
Cycl
one
V
Variable
Streaming
1,024
—
2,533
11
14
--
6,254
240
17
9
Cycl
one
V
Variable
Streaming
256
—
1,911
8
8
--
4,786
176
18
0
Cycl
one
V
Variable
Streaming
4,096
—
3,226
15
31
--
7,761
320
17
6
Strati
x V
Buffered
Burst
1,024
1
1,610
6
--
16
4,141
107
42
4
Strati
x V
Buffered
Burst
1,024
2
2,545
12
--
30
6,517
170
42
7
Strati
x V
Buffered
Burst
1,024
4
4,554
24
--
59
11,687 250
36
6
1-8
Performance and Resource Utilization
UG-FFT
2014.12.15
Altera Corporation
About This IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)