Altera FFT MegaCore Function User Manual
Page 10
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Device
Parameters
ALM
DSP
Blocks
Memory
Registers
f
MAX
(MHz)
Type
Length
Engines
M10K M20K Primar
y
Secondar
y
Cycl
one
V
Buffered
Burst
4,096
4
4,576
24
59
--
10,980 377
21
4
Cycl
one
V
Burst
Quad
Output
1,024
1
1,562
6
8
--
3,810
122
22
5
Cycl
one
V
Burst
Quad
Output
1,024
2
2,501
12
14
--
5,972
196
23
1
Cycl
one
V
Burst
Quad
Output
1,024
4
4,480
24
27
--
10,643 372
21
6
Cycl
one
V
Burst
Quad
Output
256
1
1,534
6
8
--
3,617
120
22
6
Cycl
one
V
Burst
Quad
Output
256
2
2,444
12
14
--
5,793
153
22
4
Cycl
one
V
Burst
Quad
Output
256
4
4,443
24
27
--
10,402 379
22
3
Cycl
one
V
Burst
Quad
Output
4,096
1
1,590
6
27
--
3,968
120
23
7
Cycl
one
V
Burst
Quad
Output
4,096
2
2,547
12
27
--
6,135
209
22
7
Cycl
one
V
Burst
Quad
Output
4,096
4
4,512
24
27
--
10,798 388
21
0
Cycl
one
V
Burst
Single
Output
1,024
1
673
2
6
--
1,508
83
22
2
Cycl
one
V
Burst
Single
Output
1,024
2
984
4
10
--
2,475
126
23
1
Cycl
one
V
Burst
Single
Output
256
1
639
2
3
--
1,382
159
22
9
Cycl
one
V
Burst
Single
Output
256
2
967
4
8
--
2,353
169
24
0
UG-FFT
2014.12.15
Performance and Resource Utilization
1-7
About This IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)