Altera FFT MegaCore Function - Manual (Page 19)

Figure 2-4: IP Core Generated Files
_tb.csv
_tb.spd
.cmp - VHDL component declaration file
.ppf - XML I/O pin information file
.qip - Lists IP synthesis files
.sip - Contains assingments for IP simulation files
.v or .vhd
Top-level IP synthesis file .v or .vhd
Top-level simulation file
.qsys - System or IP integration file
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
_generation.rpt - IP generation report
.debuginfo - Contains post-generation information
.html - Connection and memory map data
.bsf - Block symbol schematic
.spd - Combines simulation scripts for multiple cores
_tb.qsys
Testbench system file
.sopcinfo - Software tool-chain integration file
scripts>
IP variation files
_tb
testbench system
sim
Simulation files
synth
IP synthesis files
sim
simulation files
Simulator scripts
_tb
n
Subcore libraries
sim
Subcore
Simulation files
synth
Subcore
synthesis files
n
IP variation files
testbench files
Table 2-1: IP Core Generated Files
File Name Description
<my_ip>.qsys The Qsys system or top-level IP variation file. <my_ip> is the name
that you give your IP variation.
<system>.sopcinfo Describes the connections and IP component parameterizations in
your Qsys system. You can parse its contents to get requirements
when you develop software drivers for IP components.
Downstream tools such as the Nios II tool chain use this file.
The . sopcinfo file and the system.h file generated for the Nios II tool
chain include address map information for each slave relative to each
master that accesses the slave. Different masters may have a different
address map to access a particular slave component.
UG-FFT
2014.12.15
Files Generated for Altera IP Cores 2-5
FFT IP Core Getting Started Altera Corporation
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