About this ip core, Altera dsp ip core features, Fft ip core features – Altera FFT MegaCore Function User Manual
Page 4: About this ip core -1, Altera dsp ip core features -1, Fft ip core features -1
About This IP Core
1
2014.12.15
UG-FFT
Altera DSP IP Core Features
• Avalon
®
Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
FFT IP Core Features
• Bit-accurate MATLAB models
• Variable streaming FFT:
• Single-precision floating-point or fixed-point representation
• Radix-4, mixed radix-4/2 implementations (for floating-point FFT), and radix-2
2
single delay
feedback implementation (for fixed-point FFT)
• Input and output orders: natural order, bit-reversed or digit-reversed, and DC-centered (-N/2 to
N/2)
• Reduced memory requirements
• Support for 8 to 32-bit data and twiddle width (foxed-point FFTs)
• Fixed transform size FFT that implements block floating-point FFTs and maintains the maximum
dynamic range of data during processing (not for variable streaming FFTs)
• Multiple I/O data flow options: streaming, buffered burst, and burst
• Uses embedded memory
• Maximum system clock frequency more than 300 MHz
• Optimized to use Stratix series DSP blocks and TriMatrix memory
• High throughput quad-output radix 4 FFT engine
• Support for multiple single-output and quad-output engines in parallel
• User control over optimization in DSP blocks or in speed in Stratix V devices, for streaming, buffered
burst, burst, and variable streaming fixed-point FFTs
• Avalon Streaming (Avalon-ST) compliant input and output interfaces
• Parameterization-specific VHDL and Verilog HDL testbench generation
• Transform direction (FFT/IFFT) specifiable on a per-block basis
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