Altera FFT MegaCore Function - Manual (Page 5)

General Description
The FFT IP core is a high performance, highly-parameterizable Fast Fourier transform (FFT) processor.
The FFT IP core implements a complex FFT or inverse FFT (IFFT) for high-performance applications.
The FFT MegaCore function implements:
• Fixed transform size FFT
• Variable streaming FFT
Fixed Transform Size FFT
The fixed transform FFT implements a radix-2/4 decimation-in-frequency (DIF) FFT fixed-transform
size algorithm for transform lengths of 2m where 6 ≤ m ≤16. This FFT uses block-floating point
representations to achieve the best trade-off between maximum signal-to-noise ratio (SNR) and
minimum size requirements.
The fixed transform FFT accepts a two's complement format complex data vector of length N inputs,
where N is the desired transform length in natural order. The function outputs the transform-domain
complex vector in natural order. The FFT produces an accumulated block exponent to indicate any data
scaling that has occurred during the transform to maintain precision and maximize the internal signal-to-
noise ratio. You can specify the transform direction on a per-block basis using an input port.
Variable Streaming FFT
The variable streaming FFT implements two different types of FFT. The variable streaming FFTs
implement either a radix-2 2 single delay feedback FFT, using a fixed-point representation, or a mixed
radix-4/2 FFT, using a single precision floating point representation. After you select your FFT type, you
can configure your FFT variation during runtime to perform the FFT algorithm for transform lengths of
2m where 3 ≤ m ≤18.
The fixed-point representation grows the data widths naturally from input through to output thereby
maintaining a high SNR at the output. The single precision floating-point representation allows a large
dynamic range of values to be represented while maintaining a high SNR at the output.
The order of the input data vector of size N can be natural, bit- or digit-reversed, or -N/2 to N/2 (DC-
centered). The fixed-point representation supports a natural, bit-reversed, or DC-centered order and the
floating point representation supports a natural, digit-reversed order. The FFT outputs the transform-
domain complex vector in natural, bit-reversed, or digit-reversed order. You can specify the transform
direction on a per-block basis using an input port.
DSP IP Core Device Family Support
1-2 General Description
UG-FFT
2014.12.15
Altera Corporation About This IP Core
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