Implementing scaling, Example of scaling, Implementing scaling -3 – Altera FFT MegaCore Function User Manual
Page 45: Example of scaling -3, Table 4-1: exponent scaling values for fft / ifft
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N
P
Single Output Engine
Quad Output Engine
Max
Min
Max
2,048
6
–17
3
–16
0
4,096
6
–18
2
–17
–1
8,192
7
–20
4
–19
1
16,384
7
–21
3
–20
0
Note to
:
1. This table lists the range of exponents, which is the number of scale events
that occurred internally. For IFFT, the output must be divided by N
externally. If more arithmetic operations are performed after this step, the
division by N must be performed at the end to prevent loss of precision.
2. The maximum and minimum values show the number of times the data is
shifted. A negative value indicates shifts to the left, while a positive value
indicates shifts to the right.
Implementing Scaling
To implement the scaling algorithm, follow these steps:
1. Determine the length of the resulting full scale dynamic range storage register. To get the length, add
the width of the data to the number of times the data is shifted. For example, for a 16-bit data, 256-
point Quad Output FFT/IFFT with Max = –11 and Min = –3. The Max value indicates 11 shifts to the
left, so the resulting full scaled data width is 16 + 11, or 27 bits.
2. Map the output data to the appropriate location within the expanded dynamic range register based
upon the exponent value. To continue the above example, the 16-bit output data [15..0] from the FFT/
IFFT is mapped to [26..11] for an exponent of –11, to [25..10] for an exponent of –10, to [24..9] for an
exponent of –9, and so on.
3. Sign extend the data within the full scale register.
Example of Scaling
A sample of Verilog HDL code that illustrates the scaling of the output data (for exponents –11 to –9)
with sign extension is shown in the following example:
case (exp)
6'b110101 : //-11 Set data equal to MSBs
begin
full_range_real_out[26:0] <= {real_in[15:0],11'b0};
full_range_imag_out[26:0] <= {imag_in[15:0],11'b0};
end
6'b110110 : //-10 Equals left shift by 10 with sign extension
begin
full_range_real_out[26] <= {real_in[15]};
UG-FFT
2014.12.15
Implementing Scaling
4-3
Block Floating Point Scaling
Altera Corporation