Kontron ETXexpress-AI - Manual (Page 68)

Kontron ETXexpress-AI User’s Guide
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In compliance with the EN60950 standard, there are at least two current-
limiting devices (resistor and diode) between the battery and the consuming
component.
I
2
C Bus
The CPLD implementation connects LPC to the I 2 C controller to allow higher
speed I 2 C transactions than in previous I/O implementations.
For additional information, refer to the PICMG COM Express™ Design Guide on
the PICMG website and I
2 C application notes and JIDA specifications, which
are available on the Kontron website at
http://emdcustomersection.kontron.com/ .
See the Chapter 8, “BIOS Operation” for supported I 2 C features.
SMBus
System Management Bus (SMBbus) signals are connected to the SMBus controller,
which is located on the QM57 platform controller hub. The SMBus is a two-wire
bi-directional bus (clock and serial data) used for system management tasks
such as reading parameters from a memory card or reading temperatures and
voltages of system components.
The SMBus uses the same signaling scheme as the I 2 C bus.
PCI Bus
The Intel® QM57 PCH provides a standard PCI 2.3 32-bit/33 MHz interface on
the COM Express™ connector Type 2 implementation. The COM Express Type 6
connector does not support a PCI interface.
IDE Port
PATA (IDE) is supported on the Type 2 COM Express™ connector via a SATA-to-
PATA bridge. The Type 6 connector does not support IDE (PATA).