Kontron ETXexpress-AI - Manual (Page 63)

Kontron ETXexpress-AI User’s Guide
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4.4.8 SPI Bus Interface
The Serial Peripheral Interface (SPI) signals are connected to the QM57
platform controller hub using pins that were previously reserved on the COM
Express™ connector. The SPI interface can be used to connect two carrier
board devices, including external BIOS flash memory. The implementation of
this subsystem complies with the COM Express
TM specification. For additional
implementation information, refer to the PICMG COM Express™ Design Guide on
the PICMG website
4.4.9 LPC Bus Interface
The Low Pin Count (LPC) interface signals go to the COM Express™ X1A
connector from the QM57 PCH. The LPC low-speed interface can be used for
peripheral circuits. For example, it can be used as an external super I/O
controller to combine legacy-device support into a single IC. The
implementation of this subsystem complies with the COM Express
TM
specification. For additional implementation information, refer to the PICMG
COM Express™ Design Guide
on the PICMG website.
The LPC bus does not support DMA (Direct Memory Access) and therefore imposes
limitations for ISA bus and standard I/Os (SIOs) like floppy or LPT interface
implementations.
WARNING: When more than one device is connected to the LPC bus, a clock
buffer is required. Because of the power management of the LPC bus,
you must use great care with clock buffers that require
synchronization as they could prevent the board from booting up.
Figure 6: Standard Clock Buffer