Rockwell Automation 1746-HSCE2 Multi-Channel High Speed Counter Module - Manual (Page 98)

Publication 1746-UM002B-EN-P - August 2004
6-6 Application Examples
Ladder File 9 Continued
0012
EQU
Equal
Source A
N11:0
140<
Source B
120
120<
EQU O:1
15
I:1
15
COP
Copy File
Source
#N10:120
Dest #O:1.0
Length 8
COP
L
O:1
15
0013
EQU
Equal
Source A
N11:0
140<
Source B
130
130<
EQU O:1
15
I:1
15
COP
Copy File
Source
#N10:130
Dest #O:1.0
Length 8
COP
L
O:1
15
0014
O:1
15
I:1
15
U
O:1
15
MEQ
Masked Equal
Source
I:1.0
776<
Mask
6000h
8192<
Compare
0
0 <
MEQ ADD
Add
Source A
N11:0
140<
Source B
10
10 <
Dest
N11:0
140<
ADD
DATA_BLOCK_PTR HSCE2_XMIT
1746-HSCE2
HSCE2_XMIT
1746-HSCE2
1746-HSCE2
HSCE2_ACK
DATA_BLOCK_PTR
DATA_BLOCK_PTR
HSCE2_XMIT
1746-HSCE2
HSCE2_XMIT
1746-HSCE2
HSCE2_XMIT
1746-HSCE2
1746-HSCE2
HSCE2_ACK
HSCE2_XMIT
1746-HSCE2 1746-HSCE2
HSCE2_ACK
0015
EQU
Equal
Source A
N11:0
140<
Source B
N11:1
140<
EQU O:1
15
I:1
15
COP
Copy File
Source
#N10:140
Dest #O:1.0
Length 8
COP
B3:0
L
0
0016 L
B3:0
1
0017 END
I:1
15
I:1
14
I:1
13
HSCE2_ACK
HSCE2_FAULT
1746-HSCE2
1746-HSCE2
1746-HSCE2
HSCE2_PERR
HSCE2_ERROR
DATA_BLOCK_PTR HSCE2_XMIT
1746-HSCE2
HSCE2_INIT_DONE
1746-HSCE2
HSCE2_ACK
When the previous block is completed (transmit and acknowledge bit are reset), copy Programming
Ranges Block 8 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15).
When the previous block is completed (transmit and acknowledge bit are reset), copy Counter
Configuration Block to the HSCE2 and set transmit bit (O:e.0/15).
When HSCE2 sets its acknowledge bit (I:e.0/15), reset transmit bit (O:e.0/15),
and check HSCE2 programming error bit (I:e.0/13). If the error bit is clear,
increment the block counter to permit the next block move to start.
Note: The Counter Control Block does not require a 0-1 positive transition of the transmit bit (O:3.0/15) to operate.
If the PERR bit or HSCE2 fault bit is set, set the HSCE2 error bit (B3/1).