Rockwell Automation 1746-HSCE2 Multi-Channel High Speed Counter Module - Manual (Page 61)

Publication 1746-UM002B-EN-P - August 2004
Configuration and Programming 4-11
Figure 4.5 Counter Configuration Block Format
Programming Block Identification Bit
(Word 0, Bit 01)
This bit identifies the type of block.
TRMT: Transmit Bit
(Word 0, Bit 15)
A 0 to 1 transition starts a programming cycle.
DEBUG: Debug Mode Selection Bit
(Word 0, Bit 12)
When this bit is set, the debug mode is activated. Debug mode returns
the input data file showing current settings in the counter
configuration block. See Debug Mode Operation on page 5-7.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Word 0
TRMT
0 0
DEBUG PGM4 PGM3 PGM2 PGM1
0 0 0 0 0 0 1 0
Word 1
0 0 0 0 0 0 0 0 0 G/P Mode Input Config
CT
ype
Counter 1
Word 2 RESERVED: Must equal 0
Word 3
0 0 0 0 0 0 0 0 0 G/P Mode Input Config
CT
ype
Counter 2
Word 4 RESERVED: Must equal 0
Word 5
0 0 0 0 0 0
G/Pmode
CT
ype 0 0 0 0 0 0
G/Pmode
CT
ype
Counter 3 or 4
as indicated
Counter 4 Counter 3
Word 6 RESERVED: Must equal 0
Word 7 RESERVED: Must equal 0