Cs5490 – Cirrus Logic CS5490 User Manual
Page 38
CS5490
38
DS982F3
6.6.10 Phase Sequence Detection and Control (PSDC)
–
Page 0, Address 48
Default = 0x00 0000
DONE
Indicates valid count values reside in PSCNT[6:0].
0 = Invalid values in PSCNT[6:0]. (Default)
1 = Valid values in PSCNT[6:0].
PSCNT[6:0]
Registers the number of OWR samples from the start time to the time when the next
zero crossing is detected.
[15:6]
Reserved.
DIR
Set the zero-crossing edge direction which will stop PSCNT count.
0 = Stop count at negative to positive zero-crossing - Rising Edge. (Default)
1 = Stop count at positive to negative zero-crossing - Falling Edge.
CODE[4:0]
Write 10110 to this location to enable the phase sequence detection.
6.6.11 Checksum of Critical Registers (RegChk) – Page 16, Address 1
Default = 0x00 0000
This register contains the checksum of critical registers.
23
22
21
20
19
18
17
16
DONE
PSCNT[6]
PSCNT[5]
PSCNT[4]
PSCNT[3]
PSCNT[2]
PSCNT[1]
PSCNT[0]
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
DIR
CODE[4]
CODE[3]
CODE[2]
CODE[1]
CODE[0]
MSB
LSB
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
2
6
2
5
2
4
2
3
2
2
2
1
2
0