Cirrus Logic CS5490 - Manual (Page 24)

CS5490
24 DS982F3
6. HOST COMMANDS AND REGISTERS
6.1 Host Commands
The first byte sent to the CS5490 RX pin contains the
host command. Four types of host commands are
required to read and write registers and instruct the
calculation engine. The two most significant bits (MSBs)
of the host command defines the function to be
performed. The following table depicts the types of
commands.
Table 2. Command Format
6.1.1 Memory Access Commands
The CS5490 memory has 12-bit addresses and is
organized as P
5
P
4
P
3
P
2
P
1
P
0
A
5
A
4
A
3
A
2
A
1
A
0
in
64 pages of 64 addresses each. The higher 6 bits
specify the page number. The lower 6 bits specify the
address within the selected page.
6.1.1.1 Page Select
A page select command is designated by setting the two
MSBs of the command to binary ‘10’. The page select
command provides the CS5490 with the page number
of the register to access. Register read and write
commands access 1 of 64 registers within a specified
page. Subsequent register reads and writes can be
performed once the page has been selected.
Figure 14. Byte Sequence for Page Select
6.1.1.2 Register Read
A register read is designated by setting the two MSBs of
the command to binary ‘00’. The lower 6 bits of the read
register command are the lower 6 bits of the 12-bit
register address. After the register read command has
been received, the CS5490 will send 3 bytes of register
data onto the TX pin.
Figure 15. Byte Sequence for Register Read
6.1.1.3 Register Write
A register write command is designated by setting the
two MSBs of the command to binary ‘01’. The lower 6
bits of the register write command are the lower 6 bits of
the 12-bit register address. A register write command
must be followed by 3 bytes of data.
Figure 16. Byte Sequence for Register Write
6.1.2 Instructions
An instruction command is designated by setting the
two MSBs of the command to binary '11'. An instruction
command will interrupt any process currently running
and initiate a new process in the CS5490.
Figure 17. Byte Sequence for Instructions
These new processes include calibration, power
control, and soft reset. The following table depicts the
types of instructions. Note that when the CS5490 is in
continuous conversion mode, an unexpected or invalid
instruction command could cause the device to stop
continuous conversion and enter an unexpected
operation mode. The host processor should keep
monitoring the CS5490 operation status and react
accordingly.
Table 3. Instruction Format
Function Binary Value Note
Register
Read
0 0 A
5
A
4
A
3
A
2
A
1
A
0
A
[5:0]
specifies the
register address. Register
Write
0 1 A
5
A
4
A
3
A
2
A
1
A
0
Page Select 1 0 P
5
P
4
P
3
P
2
P
1
P
0
P
[5:0]
specifies the
page.
Instruction 1 1 C
5
C
4
C
3
C
2
C
1
C
0
C
[5:0]
specifies the
instruction.
RX Page Select Cmd.
TX
RX
DATA DATA DATA
Read Cmd.
Function Binary Value Note
Controls
0 C
4
C
3
C
2
C
1
C
0
0 00001 - Software Reset
0 00010 - Standby
0 00011 - Wakeup
0 10100 - Single Conv.
0 10101 - Continuous Conv.
0 11000 - Halt Conv. C
[5]
specifies
the instruction
type:
0 = Controls
1 = Calibrations
Calibration
1 C
4
C
3
C
2
C
1
C
0
1 00 C
2
C
1
C
0
DC Offset
1 10 C
2
C
1
C
0
AC Offset*
1 11 C
2
C
1
C
0
Gain
*AC offset calibration valid
only for current channel.
For calibration,
C
[4:3]
specifies
the type of cali-
bration.
1 C
4
C
3
C
2
C
1
C
0
1 C
4
C
3
0 0 1 I
1 C
4
C
3
0 1 0 V
1 C
4
C
3
1 1 0 I & V
For calibration,
C
[2:0]
specifies
the channel(s).
RX DATA DATA DATA Write Cmd.
RX Instruction