5 dac interface format, 6 audio word length, 7 interface control 2 (address 07h) – Cirrus Logic CS42L52 User Manual
Page 47: 1 sclk equals mclk, 2 sdout to sdin digital loopback, 5 dac interface format 6.6.6 audio word length, P 47
DS680F2
47
CS42L52
3/1/13
6.6.5
DAC Interface Format
Configures the digital interface format for data on SDIN.
Note:
Select the audio word length for Right Justified using the AWL[1:0] bits (
).
6.6.6
Audio Word Length
Configures the audio sample word length used for the data into SDIN and out of SDOUT.
Note:
When the internal MCLK/LRCK ratio is set to 125 in master mode, the 32-bit data width option
for DSP Mode is not valid unless SCLK=MCLK.
6.7
Interface Control 2 (Address 07h)
6.7.1
SCLK equals MCLK
Configures the SCLK signal source for master mode.
Note:
This bit is only valid for MCLK = 12.0000 MHz.
6.7.2
SDOUT to SDIN Digital Loopback
Configures an internal loops the signal on the SDOUT pin to SDIN.
DACDIF[1:0]
DAC Interface Format
00
Left Justified, up to 24-bit data
01
I²S, up to 24-bit data
10
Right Justified
11
Reserved
Application:
“Digital Interface Formats” on page 35
AWL[1:0]
Audio Word Length
DSP Mode
Right Justified (DAC ONLY)
00
32-bit data
24-bit data
01
24-bit data
20-bit data
10
20-bit data
18-bit data
11
16-bit data
16-bit data
Application:
7
6
5
4
3
2
1
0
Reserved
SCLK=MCLK
DIGLOOP
3ST_SP
INV_SWCH
BIASLVL2
BIASLVL1
BIASLVL0
SCLK=MCLK
Output SCLK
0
Re-timed signal, synchronously derived from MCLK
1
Non-retimed, MCLK signal
DIGLOOP
Internal Loopback
0
Disabled; SDOUT internally disconnected from SDIN
1
Enabled; SDOUT internally connected to SDIN