Cirrus Logic CS42L52 - Manual (Page 4)

4 DS680F2
CS42L52
3/1/13
4.12.2.1 Map Increment (INCR) ............................................................................................. 39
5. REGISTER QUICK REFERENCE ........................................................................................................ 40
6. REGISTER DESCRIPTION .................................................................................................................. 42
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 42
6.1.1 Chip I.D. (Read Only) ............................................................................................................ 42
6.1.2 Chip Revision (Read Only) .................................................................................................... 42
6.2 Power Control 1 (Address 02h) ...................................................................................................... 42
6.2.1 Power Down ADC Charge Pump .......................................................................................... 42
6.2.2 Power Down PGAx ................................................................................................................ 42
6.2.3 Power Down ADCx ................................................................................................................ 43
6.2.4 Power Down .......................................................................................................................... 43
6.3 Power Control 2 (Address 03h) ...................................................................................................... 43
6.3.1 Power Down ADC Override ................................................................................................... 43
6.3.2 Power Down MICx ................................................................................................................. 43
6.3.3 Power Down MIC Bias .......................................................................................................... 43
6.4 Power Control 3 (Address 04h) ...................................................................................................... 44
6.4.1 Headphone Power Control .................................................................................................... 44
6.4.2 Speaker Power Control ......................................................................................................... 44
6.5 Clocking Control (Address 05h) ...................................................................................................... 44
6.5.1 Auto-Detect ........................................................................................................................... 44
6.5.2 Speed Mode .......................................................................................................................... 45
6.5.3 32kHz Sample Rate Group ................................................................................................... 45
6.5.4 27 MHz Video Clock .............................................................................................................. 45
6.5.5 Internal MCLK/LRCK Ratio ................................................................................................... 45
6.5.6 MCLK Divide By 2 ................................................................................................................. 46
6.6 Interface Control 1 (Address 06h) .................................................................................................. 46
6.6.1 Master/Slave Mode ............................................................................................................... 46
6.6.2 SCLK Polarity ........................................................................................................................ 46
6.6.3 ADC Interface Format ........................................................................................................... 46
6.6.4 DSP Mode ............................................................................................................................. 46
6.6.5 DAC Interface Format ........................................................................................................... 47
6.6.6 Audio Word Length ................................................................................................................ 47
6.7 Interface Control 2 (Address 07h) .................................................................................................. 47
6.7.1 SCLK equals MCLK .............................................................................................................. 47
6.7.2 SDOUT to SDIN Digital Loopback ......................................................................................... 47
6.7.3 Tri-State Serial Port Interface ................................................................................................ 48
6.7.4 Speaker/Headphone Switch Invert ........................................................................................ 48
6.7.5 MIC Bias Level ...................................................................................................................... 48
6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h) ....................... 48
6.8.1 ADC Input Select ................................................................................................................... 48
6.8.2 PGA Input Mapping ............................................................................................................... 49
6.9 Analog and HPF Control (Address 0Ah) ......................................................................................... 49
6.9.1 ADCx High-Pass Filter .......................................................................................................... 49
6.9.2 ADCx High-Pass Filter Freeze .............................................................................................. 49
6.9.3 Ch. x Analog Soft Ramp ........................................................................................................ 49
6.9.4 Ch. x Analog Zero Cross ....................................................................................................... 49
6.10 ADC HPF Corner Frequency (Address 0Bh) ................................................................................ 50
6.10.1 HPF x Corner Frequency .................................................................................................... 50
6.11 Misc. ADC Control (Address 0Ch) ................................................................................................ 50
6.11.1 Analog Front-End Volume Setting B=A ............................................................................... 50
6.11.2 Digital MUX ......................................................................................................................... 50
6.11.3 Digital Sum .......................................................................................................................... 50
6.11.4 Invert ADC Signal Polarity ................................................................................................... 51
6.11.5 ADC Mute ............................................................................................................................ 51