Cirrus Logic CS4234 - Manual (Page 60)

DS899F1 60
CS4234
6.11.3 Group Delay
Sets the group delay added to the DAC1-4 path. This delay is in addition to any inherent delay in the DAC.
Modify these bits only while all of the ADCs and DACs are powered down and the DACs are in mute state.
6.12 ADC Control 1 (Address 0Fh)
6.12.1 VA Select
Scales internal operational voltages appropriately for VA level. This bit must be set appropriately for the
VA voltage level used in the application to ensure proper operation and performance of the device.
6.12.2 Enable High-Pass Filter
Enables high-pass filter for the ADC path.
6.12.3 Invert ADCx
Inverts the polarity of the ADCx signal.
GROUP
DELAY
[3:0]
Nominal
Group
Delay [ s]
Sample Rate Sample Rate Sample Rate Sample Rate Sample Rate Sample Rate
32 kHz 44.1 kHz 48 kHz 64 kHz 88.2 kHz 96 kHz
# of
Samples
Delay [ s]
# of
Samples
Delay [ s]
# of
Samples
Delay [ s]
# of
Samples
Delay [ s]
# of
Samples
Delay [ s]
# of
Samples
Delay [ s]
0000 0 0 0 0 0 0 0 0 0 0 0 0 0
0001 100 3 94 4 91 5 104 6 94 9 102 10 104
0010 150 5 156 7 159 7 146 10 156 13 147 14 146
0011 200 6 188 9 204 10 208 13 203 18 204 19 198
0100 225 7 219 10 227 11 229 14 219 20 227 22 229
0101 250 8 250 11 249 12 250 16 250 22 249 24 250
0110 275 9 281 12 272 13 271 18 281 24 272 26 271
0111 300 10 312 13 295 14 292 19 297 27 306 29 302
1000 325 10 312 14 317 15 312 21 328 29 329 31 323
1001 350 11 344 15 340 17 354 22 344 31 351 34 354
1010 375 12 375 16 363 18 375 24 375 33 374 36 375
1011 400 13 406 17 386 19 396 26 406 36 408 38 396
1100 425 14 438 18 408 20 417 27 422 38 431 41 427
1101 450 15 469 20 454 21 438 29 453 40 454 43 448
1110 475 15 469 21 476 23 479 30 469 42 476 46 479
1111 500 16 500 22 499 24 500 32 500 44 499 48 500
7 6 5 4 3 2 1 0
Reserved Reserved VA_SEL ENABLE HPF INV. ADC4 INV. ADC3 INV. ADC2 INV. ADC1
VA_SEL Must be set when VA is:
0 3.3 VDC
1 5 VDC
ENABLE HPF High Pass Filter is:
0 Disabled
1 Enabled
INV. ADCx ADCx Polarity is:
0 Not Inverted
1 Inverted