1 memory address pointer (map), 4 system clocking, 1 master clock – Cirrus Logic CS4234 User Manual

Page 26: Table 1. speed modes, Cs4234

DS899F1

CS4234

Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 0010xxx1 (chip address and read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.

Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.

4.3.1

Memory Address Pointer (MAP)

The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudocode above for implementation details.

4.3.1.1

Map Increment (INCR)

The CS4234 has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR
is set to ‘0’, MAP will stay constant for successive I²C reads or writes. If INCR is set to ‘1’, MAP will auto-
increment after each byte is read or written, allowing block reads or writes of successive registers.

4.4

System Clocking

The CS4234 will operate at sampling frequencies from 30 kHz to 100 kHz. This range is divided into two
speed modes as shown in

Table 1

The serial port clocking must be changed while all PDNx bits are set. If the clocking is changed otherwise,
the device will enter a mute state, see

Section 4.8 on page 47

4.4.1

Master Clock

The ratio of the MCLK frequency to the sample rate must be an integer. The FS/LRCK frequency is equal
to F

, the frequency at which all of the slots of the TDM stream or channels in Left Justified or I²S formats

are clocked into or out of the device. The

Speed Mode

and

Master Clock Rate

bits configure the device

to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode.

Table 2

illus-

trates several standard audio sample rates and the required MCLK and FS/LRCK frequencies.

The CS4234 has an internal fixed ratio PLL. This PLL is activated when the

“MCLK RATE[2:0]” bits in the

"Clock and SP Sel." register

are set to either 000 or 001, corresponding to 256x or 384x. When in either

of these two modes, the PLL will activate to adjust the frequency of the incoming MCLK to ensure that the
internal state machines operate at a nominal 24.576 MHz rate. As is shown in the

Typical Current Con-

sumption

table, activation of the PLL will increase the power consumption of the CS4234.

Mode

Sampling Frequency

Single-Speed

30-50 kHz

Double-Speed

60-100 kHz

Table 1. Speed Modes