Cirrus Logic CS4234 - Manual (Page 55)

DS899F1 55
CS4234
6.5 Serial Port Control (Address 08h)
6.5.1 Invert SCLK
When set, this bit inverts the polarity of the SCLK signal.
6.5.2 DAC5 Input Source
Sets which portion of data is to be routed to the DAC5 data path.
6.5.3 Serial Port Format
Sets the format of both the incoming serial data signals and outgoing serial data signal.
6.5.4 Serial Data Output Sidechain
Setting this bit enables the SDOUT1 side chain feature. In this mode, the samples from multiple devices
can be coded into one TDM stream. See
Section 4.6.2 ADC Path for more details.
6.5.5 Master / Slave
Setting this bit places the CS4234 in master mode, clearing it places it in slave.
I²S and Left Justified are the only available serial port formats if the CS4234 is placed into Master Mode.
7 6 5 4 3 2 1 0
INV SCLK DAC5 SOURCE[2:0] SP FORMAT[1:0] SDO CHAIN MASTER/SLAVE
INV SCLK SCLK is:
0 Not Inverted
1 Inverted
DAC5 SOURCE Data is routed into the DAC5 path from:
000 LSB’s of slots 1-3 of the TDM stream on SDIN1
001 LSB’s of slots 5-7 of the TDM stream on SDIN1
010 LSB’s of slots 9-11 of the TDM stream on SDIN1
011 LSB’s of slots 13-15 of the TDM stream on SDIN1
100 Mask bits are used to determine the input signal in the DAC5 path. See Section 4.6.5 for details.
101 Reserved
110 Reserved
111 Reserved
SP FORMAT Format is:
00 Left Justified
01 I 2 S
10 TDM (Slave Mode Only)
11 Reserved
SDO CHAIN Sidechain is:
0 Disabled
1 Enabled
MASTER / SLAVE CS4234 is in:
0
Slave Mode
1 Master Mode