Cirrus Logic CS4234 - Manual (Page 27)

DS899F1 27
CS4234
Note:
34. 128x and 192x ratios valid only in Left Justified or I²S formats.
4.4.2 Master Mode Clock Ratios
As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK
is equal to F
S
and SCLK is equal to 64x F
S
as shown in Figure 13 . TDM format is not supported in Master
Mode.
The resulting valid master mode clock ratios are shown in Table 3 below.
4.4.3 Slave Mode Clock Ratios
In Slave Mode, SCLK and FS/LRCK operate as inputs. The FS/LRCK clock frequency must be equal to
the sample rate, F
S
, and must be synchronously derived from the supplied master clock, MCLK.
FS/LRCK (kHz) MCLK (MHz)
128x
(Note 34)
192x
(Note 34)
256x 384x 512x
32 - - 8.1920 12.2880 16.3840
44.1 - - 11.2896 16.9344 22.5792
48 - - 12.2880 18.4320 24.5760
64 8.1920 12.2880 16.3840 - -
88.2 11.2896 16.9344 22.5792 - -
96 12.2880 18.4320 24.5760 - -
Mode DSM SSM
Table 2. Common Clock Frequencies
SSM DSM
MCLK/F
S
256x, 384x, 512x 128x, 192x, 256x
SCLK/F
S
64x 64x
Table 3. Master Mode Left Justified and I²S Clock Ratios
ч512
ч256
ч8
ч4
00
01
00
01
FS/LRCK
SCLK
000
001
010
x2
ч1.5
ч1
MCLK Speed Mode Bits
MCLK Rate Bits
x2
PLL active
Figure 13. Master Mode Clocking