GW Instek APS-1102 LabVIEW Driver User Manual - Manual (Page 37)

2.14 PROGram Subsystem
2-29
GW APS-1102 OPC.vi
When all operations have been completed, this sets the standard event register’s OPC bit (BIT0).
*OPC? returns “1” when all operations have been completed. However, the standard event register
OPC bit is not cleared zero *OPC? is executed.
Query OPC
When Read = True, outputs the OPC bit content set for the APS-1102. When Read = False,
“999” is set.
GW APS-1102 RCL.vi
This recalls the status information stored to memory by *SAV. The selection range for the recall
memory is 1 to 30. However, recall is disabled when output is on. ([1,"Invalid with output on"] error
occurs.)
RCL
This outputs the standard event enable register. The default setting is “1”.
GW APS-1102 Reset.vi
This resets the device to its factory settings. However, reset cannot be executed when output is on.
([1, “Invalid with output on”] error occurs.)
GW APS-1102 SAV.vi
This stores the current status information in the memory. The memory storage range is 1 to 30.
SAV
This sets the standard event enable register. The default setting is “1”.
GW APS-1102 SRE.vi
This sets the service request enable register. The setting range is 0 to 178.
SRE
This sets the service request enable register. The default setting is “0”.