Rainbow Electronics MAX3540 - Manual (Page 13)

MAX3540
Complete Single-Conversion Television Tuner
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Interpolating Tracking Filter Coefficients
The TFS[7:0] and TFP[5:0] bits must be reprogrammed
for each channel frequency to optimize performance.
The optimal settings for each channel can be calculated
from the ROM table data using the equations below.
VHF LO filter:
VHF High filter:
UHF filter:
Where:
f RF = operating frequency in MHz
TFS = decimal value of the optimal TFS[7:0]
setting (Table 9) for the given operating frequency
TFP = decimal value of the optimal TFP[5:0] setting
(Table 10) for the given operating frequency
LS0, LS1, LP0, LP1, HS0, HS1, HP0, HP1, US0, US1,
UP0, and UP1 = the decimal values of the ROM
table coefficients (Table 16).
IF Overload Detector
The MAX3541 includes a broadband IF overload detec-
tor, which provides an indication of the total power pre-
sent at the RF input. The overload-detector output
voltage is compared to a reference voltage and the dif-
ference is amplified. This error signal drives an open-
collector transistor whose collector is connected to the
IFOVLD pin, causing the IFOVLD pin to sink current.
The nominal full-scale current sunk by the IFOVLD pin
is 300μA. The IFOVLD pin requires a 10kΩ pullup resis-
tor to V
CC .
The IF overload detector is calibrated at the factory to
attack at 0.6V
P-P at IFOUT1. Upon power-up, the base-
band processor must read OD[2:0] from the ROM table
and store it in the IFVOLD register.
Closed-Loop RF Gain Control
Closed-loop RF gain control can be implemented by
connecting the IFOVLD output to the RFAGC input.
Using a 10kΩ pullup resistor on the IFOVLD pin, as
shown in the
Typical Application Circuit , results in a
nominal 0.5V to 3V control voltage range.
VCO and VCO Divider Selection
The MAX3540 frequency synthesizer includes three VCOs
and eight VCO sub-bands to guarantee a 2160MHz to
4400MHz VCO frequency range. The frequency synthesiz-
er also features an additional VCO frequency divider,
which must be programmed to either 4, 8, 16, or 32
through the VDIV[1:0] bits in the VCO register based on
the channel being received. Table 5 describes how the
VDIV[1:0] bits should be programmed for each band of
operation.
To ensure PLL, lock the proper VCO and VCO sub-band
for the channel being received, which must be chosen by
iteratively selecting a VCO and VCO sub-band then read-
ing the LD[2:0] bits to determine if the PLL is locked. Any
reading from 001 to 110 indicates the PLL is locked. If
LD[2:0] reads 000, the PLL is unlocked and the selected
VCO is at the bottom of its tuning range; a lower VCO sub-
band must be selected. If LD[2:0] reads 111, the PLL is
unlocked and the selected VCO is at the top of its tuning
range; a higher VCO sub-band must be selected. The
VCO and VCO sub-band settings should be progressively
increased or decreased until the LD[2:0] reading falls in
the 001 to 110 range.
Due to overlap between VCO sub-band frequencies, it is
possible that multiple VCO settings can be used to tune to
the same channel frequency. System performance at a
given channel should be similar between the various pos-
sible VCO settings, so it is sufficient to select the first VCO
and VCO sub-band that provides lock.
Layout Considerations
The MAX3540 EV kit can serve as a guide for PCB layout.
Keep RF signal lines as short as possible to minimize
losses and radiation. Use controlled impedance on all
high-frequency traces. The exposed paddle must be sol-
dered evenly to the board’s ground plane for proper
operation. Use abundant vias beneath the exposed pad-
dle for maximum heat dissipation. Use abundant ground
vias between RF traces to minimize undesired coupling.
TFP INT 10
[(1.6
UP0
256
0.8)
UP1
6 =
+ × + − + ( . 1 4
4 4
0.8 ) f 10 ]
RF
-3
10
Ч Ч Ч
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
−
TFS INT 10
[(3
US0
256
)
US1
64
0.8 )
=
+ + − + Ч Ч ( . 2 6 f 10 ]
RF
-3
20
×
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
−
TFP INT 10
[(1.6
HP0
16
0.8)
HP1
16 =
+ Ч + − + Ч ( . 1 5 0 0.6 ) f 10 ]
RF
-3
10
Ч Ч
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
−
TFS INT 10
[(2.8
HS0
16
0.8)
HS1
16
0.8 )
=
+ Ч + − + Ч ( . 4 2 ЧЧ Ч
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
−
f 10 ]
RF
-3
20
TFP INT 10
[(1.6
LP0
64
0.4)
LP1
16
2
=
+ Ч + − + Ч ( 6 )) f 10 ]
RF
-3 Ч Ч
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
TFS 10 (2.4
LS0
64
0.6)
LS1
16
2) f
RF 1
= + Ч + − + Ч Ч
Ч
( . 8 5
0 0
-3
⎡
⎣⎢ ⎤
⎦⎥