Rainbow Electronics DS1841 - Manual (Page 15)

DS1841
Temperature-Controlled, NV, I 2 C,
Logarithmic Resistor
______________________________________________________________________________________ 15
Writing multiple bytes to a slave: I 2 C write operations
of multiple bytes can also be performed. During a sin-
gle write sequence, up to 8 bytes in one page can be
written at one time. If more than eight bytes are trans-
mitted in the sequence, then only the last eight trans-
mitted bytes are stored. After the last physical memory
location in a particular page (8-byte page write), the
address counter automatically wraps back to the first
location in the same page for subsequent byte write
operations.
Acknowledge polling: Any time a EEPROM byte is
written, the DS1841 requires the EEPROM write time
(t
W ) after the STOP condition to write the contents of
the byte to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the
DS1841, which allows communication to continue as
soon as the DS1841 is ready. The alternative to
acknowledge polling is to wait for a maximum period of
t
W to elapse before attempting to access the device.
Reading a single byte from a slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read opera-
tion occurs at the present value of the memory address
counter. To read a single byte from the slave, the master
generates a START condition, writes the slave address
byte with R/W = 1, reads the data byte with a NACK to
indicate the end of the transfer, and generates a STOP
condition. However, since requiring the master to keep
track of the memory address counter is impractical, the
following method should be used to perform reads from
a specified memory location.
Reading multiple bytes from a slave: The read opera-
tion can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master
reads the last byte it must NACK to indicate the end of
the transfer and generates a STOP condition. During a
single read sequence of multiple bytes, after the last
address counter position of FFh is accessed, the
address counter automatically wraps back to the first
location, 00h. Read operations can continue indefinitely.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-
SLAVE
ADDRESS*
START
START
0 1 0 1 0 A1 A0 R/W
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MSB LSB MSB LSB MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
READ/
WRITE REGISTER ADDRESS
b7 b6 b5 b4 b3 b2 b1 b0
DATA
STOP
SINGLE-BYTE WRITE
-WRITE CONTROL
REGISTER 0 TO 00h
SINGLE-BYTE READ
-READ TEMPERATURE
REGISTER
TWO-BYTE WRITE
- WRITE LUT VALUES FOR
REGISTERS 80h AND 81h
START
REPEATED
START
51h DATA
MASTER
NACK
STOP 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0
0Ch
0 1 0 1 0 0 0 1
0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0
50h 02h
STOP
TEMP
EXAMPLE I 2 C TRANSACTIONS (WHEN A0 AND A1 ARE CONNECTED TO GND)
TYPICAL I 2 C WRITE TRANSACTION
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
0 0 0 0 0 0 0 0
50h
A)
B)
C)
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0
50h 80h
STOP
40h
0 1 0 0 0 0 0 0
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
50h
0 1 0 1 0 0 0 0
SLAVE
ACK
TWO-BYTE READ
- READ LUT REGISTERS
80h AND 81h D)
START 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0
50h 80h
STOP
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MASTER
ACK
51h
0 1 0 1 0 0 0 1
DATA DATA
MASTER
ACK
REG81h REG80h
REPEATED
START
Figure 4. I 2 C Communication Examples