Rainbow Electronics ISD5216 - Manual (Page 52)

I5216 SERIES
Advanced Information
PRELIMINARY
Publication Release Date: November 30, 2001
- 52 Revision A1
SAMPLE PC LAYOUT FOR PDIP
The PDIP package is illustrated from the top. PC board traces and the three chip capacitors are on the
bottom side of the board.
1
C1
C2
C3
Note 1
Note 2
V
C
C
D
MCLK
V
SSA
C1=C2=C3=0.1 uF chip Capacitors
To
V
CCA
Analog Ground Note 3
V
S
S
D
Note 3 (Digital Ground)
Note 1: V
SSD
traces should be kept
separated back to the V
SS
supply feed
point.
Note 2: V
CCD
traces should be kept
separated back to the V
CC
supply feed
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
V
CCA
and V
CCD
supplies will also need
filter capacitors ( typ . 50 to 100 uF ).
1
C1
C2
C3
Note 1
Note 2
V
C
C
D
MCLK
V
SSA
C1=C2=C3=0.1 uF chip Capacitors
To
V
CCA
Analog Ground Note 3
V
S
S
D
Note 1: V
SSD
traces should be kept
separated back to the V
SS
supply feed
point.
Note 2: V
CCD
traces should be kept
separated back to the V
CC
supply feed
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
V
CCA
and V
CCD
supplies will also need
filter capacitors ( typ . 50 to 100 uF ).