Rainbow Electronics ISD5216 - Manual (Page 26)

I5216 SERIES
Advanced Information
PRELIMINARY
Publication Release Date: November 30, 2001
- 26 - Revision A1
PLAYBACK MODE
The command sequence for an analog Playback operation can be handled several ways. One
technique is to do a Load Address (81h), which requires sending a total of four bytes, followed by a
Play Analog, which is a Command Byte (A8h) preceded by the Slave Address Byte. This is a total of six
bytes plus the times for Start, ACK, and Stop.
Another approach for an analog Playback operation is via a single four byte exchange, which consists
of the Slave Address (80h), the Command Byte (A9h) for Play Analog @ Address, and the two address
bytes.
RECORD MODE
The command sequence for an Analog Record is a four byte sequence consisting of the Slave
Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes.
(See
I
2
C Interface on page 17 for more detail.)
FEED THROUGH MODE
This diagram shows the part of the I5216 block diagram that is used in Feed Through Mode. The rest of the chip
will be powered down to conserve power. Note that the Microphone and Speaker +/– paths are differential
DAC
ADC
µ
/A-Law
Compressor
µ
/A-Law
Expander
PC
M
I
nt
er
fa
ce
2
(LAW1,LAW0)
SDI
SDIO
WS
SCK
3
(CIG2,CIG1,CIG0)
3
(COG2,COG1,COG0)
MIC+
MIC -
INP+
INP-
SUM2+
SUM2-
C
ODE
C
In
M
u
x
Input
GAIN
SP+
SP-
SPEAKER
FILTO+
Ou
tp
u
t M
U
X
Spkr.
AMP
(OPA1,OPA0)
2
(OPS1,OPS0)
2
VOL+
SUM2+
DAO+
DAO-
SUM2-
VOL-
FILTO-
2
(LAW1,LAW0)
1
(I2S0)
3
(DAPD,HSR0,MUTE)
4
(ADPD,HSR0,HPF0,MUTE)
(CDI1,CDI0)
2
Output
GAIN
DAC
ADC ADC
µ
/A-Law
Compressor
µ
/A-Law
Expander
PC
M
I
nt
er
fa
ce
2
(LAW1,LAW0)
2
(LAW1,LAW0)
SDI SDI
SDIO SDIO
WS WS
SCK SCK
3
(CIG2,CIG1,CIG0)
3
(COG2,COG1,COG0)
MIC+
MIC -
INP+
INP-
SUM2+
SUM2-
C
ODE
C
In
M
u
x
MIC+
MIC -
INP+
INP-
SUM2+
SUM2-
MIC+
MIC -
INP+
INP-
SUM2+
SUM2-
C
ODE
C
In
M
u
x
Input
GAIN
SP+
SP-
SPEAKER
FILTO+
Ou
tp
u
t M
U
X
Spkr.
AMP
(OPA1,OPA0)
2
(OPS1,OPS0)
2
VOL+
SUM2+
DAO+
DAO-
SUM2-
VOL-
FILTO-
2
(LAW1,LAW0)
2
(LAW1,LAW0)
1
(I2S0)
1
(I2S0)
3
(DAPD,HSR0,MUTE)
4
(ADPD,HSR0,HPF0,MUTE)
(CDI1,CDI0)
2
Output
GAIN