Rainbow Electronics ISD5216 - Manual (Page 25)

I5216 SERIES
Advanced Information
PRELIMINARY
Publication Release Date: November 30, 2001
-25 Revision A1
POWER-UP SEQUENCE
This sequence prepares the I5216 for an operation to follow, and waits for the Tpud time before
sending the next command sequence.
1. Send I
2
C Start.
2. Send one byte 10000000 {Slave Address, R/W = 0} 80h.
3. Slave ACK.
4. Wait for SCL High.
5. Send one byte 10000000 {Command Byte = Power Up} 80h.
6. Slave ACK.
7. Wait for SCL High.
8. Send I
2
C Stop.
SET MASTER CLOCK DIVISION RATIO
The I5216 product has two Master Clock configuration bits that allow four possible Master Clock
frequencies. The Master Clock Division ratios can be set by bits CKD2 and CKDV. These are bits D12
and D8 of CFG2, respectively. The combination of these bits, with the sample rate bit HSR0, also sets
the CODEC sample frequency.
Master Clock Possible Settings
F
MCLK
HSR0 (D5)
(CFG2)
CKD2 (D12)
(CFG2)
CKDV (D8)
(CFG2)
F
SCODEC
13.824 MHz 0 0 0 8 kHz
20.48 MHz 0 0 1 11.852 kHz*
27.648 MHz 0 1 0 8 kHz
40.96 MHz 0 1 1 11.852 kHz*
13.824 MHz 1 0 0 32 kHz*
20.48 MHz 1 0 1 44.1 - 48 kHz
27.648 MHz 1 1 0 32 kHz*
40.96 MHz 1 1 1 44.1-48 kHz
*not tested