Rainbow Electronics ISD5216 - Manual (Page 46)

I5216 SERIES
Advanced Information
PRELIMINARY
Publication Release Date: November 30, 2001
- 46 Revision A1
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing
mode. See the
Timing Parameters table on page 55 for RAC timing information at other sample rates.
When a record command is first initiated, the RAC pin remains HIGH for an extra T
RACLO
period in
order to load sample and hold circuits internal to the device. The RAC pin can be used for message
management techniques.
1 ROW
RAC Waveform
During Message Cueing
500 usec
T
RAC
15.6 us
T
RACLO
RAC Waveform
During Digital Erase
INT (Interrupt)
INT is an open drain output pin. The Winbond I5216 Interrupt pin goes LOW and stays LOW when an
Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that gives a status byte out the SDA line.
MCLK (Master Clock Input)
The Master clock input for the Winbond I5216 product has an internal pull-down device. Normally, the
Winbond I5216 ChipCorder section is operated at one of four internal rates selected for its internal
oscillator by the Sample Rate Select bits. If the internal oscillator is powered down (configuration bit
OSPD set to ONE), the device is clocked through the MCLK pin as shown in the section
I5216 Analog
Structure (right half) description on page 36.
.
25 µsec
1
.
25 µsec