Rainbow Electronics ISD5216 - Manual (Page 45)

I5216 SERIES
Advanced Information
PRELIMINARY
Publication Release Date: November 30, 2001
- 45 Revision A1
Notes:
1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low
Address Byte will be ignored.
2. I 2 C bus is released while erase proceeds. Other devices may use the bus until it is time
to execute the STOP command that causes the end of the Erase operation.
3. Host processor must count RAC cycles to determine where the chip is in the erase
process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end of
each erased row. The erase of the “next” row begins with the rising edge of RAC. See
the Digital Erase RAC timing diagram on page 46.
4. When the erase of the last desired row begins, the following STOP command (Command
Byte = 80 hex) must be issued. This command must be completely given, including
receiving the ACK from the Slave before the RAC pin goes HIGH .25 microseconds before
the end of the row
.
PIN DETAILS
DIGITAL I/O PINS:
SCL (SERIAL CLOCK LINE)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to
Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over
the Serial Data Line.
SDA (SERIAL DATA LINE)
The Serial Data Line carries the data between devices on the I 2 C interface. Data must be valid on this
line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bi-
directional line requiring a pull-up resistor to Vcc.
RAC (ROW ADDRESS CLOCK)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency
the duration of this period is 256 ms. there are 1888 pages of memory in the Winbond I5216 device.
RAC stays HIGH for 248 ms and goes LOW for the remaining 8 ms before it reaches the end of the
page.
1 ROW
RAC Waveform
During 8 KHz Operation
256 msec
T
RAC
8 msec
T
RACLO