Motorola ATCA-717 - Manual (Page 144)

Maps and Registers FPGA Registers
144 PENT/ATCA−717
Clock Synchronization Interface Registers
These registers are related to the clock synchronization building block of the blade. These
registers are primarily used to:
aa
S Select system clock 1 or 2 from back plane
S Select system or reference clock for DPLL input
S Enable reference clocks A and B to the backplane
S Select recovered clock source
S Determine programmable reference clock divider value
S Determine reference clock pulse width
Note: a Motorola offers a device driver to access the clock synchronization interface.
Instead of directly accessing the clock synchronization interface via the registers
described in this section, it is strongly recommended to use this driver. Ask your local
Motorola representative for details.
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The following clock synchronisation interface registers are available:
Table 28: Clock Synchronisation Interface Registers
Index Address Register
30
16
SPI Address register
31
16
SPI Data register
32
16
DPLL Input Select and Control register
33
16
Reference Clock Divider register
34
16
Lower Reference Clock Divder register
35
16
Upper Reference clock Divider register
36
16
Reference Clock Pulse Width register
SPI Interface Registers
The used DPLL device ACS8525 from SEMTECH provides a Serial Peripheral Interface
(SPI) which provides external access for device setup and controlling. Software that
wishes to access the DPLL device has to first set the desired address in the SPI Address
register followed by either a read or write access to the SPI data register. For details about
configuring the DPLL device, refer to its data sheet.
a