Motorola ATCA-717 User Manual
Page 125
Clock Synchronization Interface
Devices’ Features and Data Paths
PENT/ATCA−717
125
S 8 kHz frame clock/pulse with programmable pulse width and polarity
(SYNC_0,1,2,3))
S Automatic hit−less switch−over if one system clock fails
S Activity monitor for system clocks
S Phase build−out for output clock phase continuity during switch−over
S Meets jitter requirements up to OC−3 line rates
S Programmable reference clock divider
The DPLL is clocked by an external oscillator running at 12.8 MHz. Two clock buffers
provide a separate clock and synchronization signal for each of the four on−board PMC
sites. The FPGA contains extensions which are related to the clock synchronization
building block. Some of these extensions include registers that are accessible via the host
and which allow to control and monitor the functionality of the clock synchronization
building block. For details refer to
a
section "Clock Synchronization Interface Registers" on
a