Motorola ATCA-717 - Manual (Page 115)

FPGA Devices’ Features and Data Paths
PENT/ATCA−717 115
FPGA
The FPGA implements the following functions: aaaaa
S LPC interface
S IPMC interface
S Clock synchronization extensions
S Reset controller
S Interrupt routing unit
S Miscellaneous glue logic
S Ethernet switch interface
The FPGA loads its configuration stream from one of two EEPROMs which are connected
to the FPGA. One EEPROM serves as default, the second as backup EEPROM. The IPMC
controls which EEPROM the configuration stream is loaded from. After IPMC startup the
FPGA loads its configuration stream from the default EEPROM. An IPMI System Boot
Options command allows to select between default and backup EEPROM. For details
about switching between default and backup FPGA refer to
the
a PENT/ATCA−715/717/7105/7107: Control via IPMI Programmer’s Guide a which can be
downloaded from the Motorola literature site. aaa
LPC Interface
The LPC interface is compliant to the Intel LPC specification 1.1 and connects the FPGA to
the South Bridge.
a
IPMC Interface
The FPGA is connected to the on−board IPMC and implements the following IPMC
related features:
S Two Block Transfer interfaces
S Port 80 register
S IPMC extensions
Block Transfer Interfaces
Two Block Transfer interfaces (BT) reside inside the FPGA. Each provides one control and
status register, two 64−byte FIFOs and an interrupt mask register. Both BT interfaces are