Measurement Computing DaqBoard 1000 Series - Manual (Page 77)

Note: Specifications subject to change without notice. 889094 Specifications – DaqBoard/1000 Series 6-3
Analog Outputs
Applicable to DaqBoard/1000; does not apply to DaqBoard/1005
Two analog output channels are updated synchronously relative to scanned inputs, and clocked from
either an internal onboard clock, or an external clock source. Analog outputs can also be updated
asynchronously, independent of any other scanning in the system. Bus mastering DMA provides
CPU and system-independent data transfers, ensuring accurate outputs that are irrespective of other
system activities. Streaming from disk or memory is supported, allowing continuous, nearly-infinite
length, waveform outputs (limited only by available PC system resources).
Channels: 2 DAC channels (DAC0, DAC1)
Resolution: 16 bits
Output voltage range: ±10 V
Digital Feedthru: 50 mV when updated
Output current: ±10 mA
Offset error: ±0.0045 V maximum
Gain error: ±0.01%
Update rate: 100 kHz maximum, 1.5 Hz minimum (no minimum with external clock)
Settling Time: 10 µs maximum to 1 LSB for full-scale step
Clock Sources: 4 programmable
1. Onboard D/A clock, independent of scanning input clock
2. Onboard scanning input clock
3. External D/A input clock, independent of external scanning input clock
4. External scanning input clock
Digital I/O Applicable to DaqBoard/1000, /1005
Channels: 24, expandable to 208 with external DBK options
Input Scanning Modes: 2 programmable
1.
Asynchronous, under program control at any time relative to input scanning
2.
Synchronous with input scanning
Ports: 3 x 8-bit (82C55 emulation). Each port is programmable as input or output.
Input Characteristics: 100 Ω series, 20 pF to common
Input protection: ±8 kV ESD clamp diodes parallel
I/O levels: TTL
Sampling/Update rate: 200 kHz maximum
Output Characteristics: Output 12 mA per pin, 200 mA total continuous (per bank of 24 outputs)
Counters Applicable to DaqBoard/1000, /1005
Counter inputs can be scanned synchronously along with analog and digital scanned inputs, based
either on internal programmable timer, or an external clock source. Bus mastering DMA provides
CPU and system-independent data transfers, insuring data acquisition performance irrespective of
other system activities. Counters can be configured to clear when read, or to totalize and clear under
program control.
Channels: 4 x 16-bit, cascadable as 2 x 32-bit
Frequency Measurement Rate: 10 MHz maximum
Input Signal Range: -15 V to +15 V
Input Characteristics: 2.7 kΩ series in parallel with 20 pF to common and 10 kΩ to +5 V
Input protection: ±8 kV ESD clamp diodes parallel
Trigger Level: TTL
Minimum pulse width: 50 ns high, 50 ns low