BECKHOFF ET1100 - Manual (Page 44)

EtherCAT IP Core for Xilinx FPGAs
40 Slave Controller – Application Note FAQ
5.4 Hardware issues
If the hardware is not working, the following functions should be tested, e.g., by routing signals to
LEDs or using ChipScope or external measurement equipment.

Reset: polarity issues are common, probe exactly the signal which enters the IP Core.

Clock: Are all clocks connected, valid and synchronous (25 MHz and 100 MHz)? Is the PLL
locked?

Turn off MI link detection and configuration for testing if the PHY does not need to be
programmed.

Check if all FPGA pins are located correctly.

Is the Timing report error-free?