BECKHOFF ET1100 - Manual (Page 3)

CONTENTS
Slave Controller – Application Note FAQ III
CONTENTS
1 Introduction 1
2 Frequently unasked questions 2
2.1 What information should I provide when I need support? 2
3 General Issues 3
3.1 Where can I find documentation updates? 3
3.2 ESC clock source accuracy: Is 25 ppm necessary? 3
3.3 Why should port 0 never be an unused port? 3
3.4 Link/Activity LEDs shows strange behavior 3
3.5 Can slaves communicate without SII EEPROM / invalid SII EEPROM content? 3
3.6 Do I need the complete XML ESI description for simple PDI read/write tests? 3
3.7 What do I do with unused ports (EBUS/MII) 4
3.8 Resetting ESC, PHYs, and µController 4
3.9 Should I enable Enhanced Link Detection? 5
3.10 Why must I configure the PHYs for auto-negotiation instead of forcing 100
Mbit+FD? 5
3.11 What is TX Shift and Auto TX Shift? 5
3.12 Frames are lost / communication errors are counted 6
3.12.1 Configuring TwinCAT to show the ESC error counters 6
3.12.2 Reduce the complexity 6
3.12.3 Basic error counter interpretation 7
3.12.4 Error counter interpretation guide 8
3.13 PDI Performance 10
3.14 Interrupts 11
3.14.1 µControllers with edge-triggered Interrupt / only the first interrupt is
processed 11
3.14.2 Polling and Interrupt handling 11
3.15 Distributed Clocks: Resolution, Precision, Accuracy 12
3.16 Hardware not working 13
4 EtherCAT IP Core for Altera FPGAs 14
4.1 Licensing issues 14
4.1.1 Check license status 14
4.1.2 Compare license file and Quartus II License Setup 15
4.1.3 No license found 16
4.1.4 License expired 17
4.1.5 OpenCore Plus License Identification 18
4.2 Implementation issues 19
4.2.1 MegaWizard generation 19
4.2.2 Analysis & Synthesis 20
4.2.2.1 Checking the actual EtherCAT IP Core configuration 20
4.2.2.2 Vendor ID package is in the project, but not on the disk 21