BECKHOFF ET1100 - Manual (Page 4)

CONTENTS
IV Slave Controller – Application Note FAQ
4.2.2.3 Vendor ID package is not in the project 21
4.2.2.4 Important logic parts or I/O signals are optimized away,
hardware does not work
22
4.2.3 Library files are not copied to project (reference designs) 23
4.2.4 Additional signals (SIM_FAST, PHY_OFFSET) in the pinout report 24
4.2.5 Timing closure issues 26
4.2.5.1 OpenCore Plus logic does not achieve timing
(altera_reserved_tck)
26
4.2.5.2 General timing closure issues 26
4.3 Hardware issues 27
4.4 OpenCore Plus design stops operating too early 27
5 EtherCAT IP Core for Xilinx FPGAs 28
5.1 Project navigator/EDK crashes 28
5.2 Licensing issues 29
5.2.1 Check license status 29
5.2.2 Compare license file and Xilinx License Configuration Manager 30
5.2.3 No license found 31
5.2.4 Evaluation License Identification 32
5.2.4.1 Installed license file 32
5.2.4.2 Installed EtherCAT IP Core 32
5.2.5 Vendor ID package missing 33
5.3 Implementation issues 34
5.3.1 XST 34
5.3.1.1 RSA decryption keys missing (ISE) 34
5.3.1.2 RSA decryption keys missing (EDK) 35
5.3.1.3 Checking the actual EtherCAT IP Core configuration 36
5.3.2 Place & Route 37
5.3.2.1 CLOCK_DEDICATED_ROUTE=FALSE with SPI reference
design
37
5.3.3 PlanAhead 38
5.3.3.1 PlanAhead implementation/floorplaning/analysis is not possible38
5.3.4 General timing closure issues 39
5.4 Hardware issues 40
6 Appendix 41
6.1 Logging Error Counters in TwinCAT 41
6.2 TwinCAT hints 47
6.3 Support and Service 48
6.3.1 Beckhoff’s branch offices and representatives 48
6.4 Beckhoff Headquarters 48