BECKHOFF ET1100 - Manual (Page 28)

EtherCAT IP Core for Altera FPGAs
24 Slave Controller – Application Note FAQ
4.2.4 Additional signals (SIM_FAST, PHY_OFFSET) in the pinout report
Sometimes Altera Quartus II routes internal signals of the EtherCAT IP Core up to the top level design
and finally to FPGA pins if OpenCore Plus evaluation is used. This issue does not occur with the full
license, and it was not observed in recent Quartus II versions. It is not an EtherCAT IP Core issue, but
a Altera Quartus II issue.
Typically, the names of these input signals look like this (Compilation report – Fitter – Resource
Section – Input Pins) – note the extra path information, which is not common to other FPGA I/Os:

EtherCAT_DigitalIO:inst1|ETHERCAT_IPCORE:EtherCAT_IPCore_inst|SIM_FAST

EtherCAT_DigitalIO:inst1|ETHERCAT_IPCORE:EtherCAT_IPCore_inst|PHY_OFFSET
The pin location is assigned by the fitter, so the actual values of these signals are not predefined. The
intentional default value of t
hese internal signals is ‘0’. Depending on the actual pin state, the signals
might become ‘1’, which causes unwanted behavior of the IP Core. The SIM_FAST signal will e.g.
disturb EEPROM and MII interface functions, if it is ‘1’.
This is a known bug of Altera Quartus, which is currently not fixed. The bug was observed e.g. with
Quartus II 7.2 SP3, and EtherCAT IP Core V2.0.0, and the EL9800_DIGI_EP1C12F256 reference
design. Other Quartus versions and other IP Core versions have also been subject to this issue.
Work-around
You have to edit the *.vhd wrapper file generated by the MegaWizard Plugin, e.g.
“EtherCAT_DigitalIO.vhd” for the EL9800_DIGI_EP1C12F256 reference design, with a text editor.
In the following example, SIM_FAST and PHY_OFFSET occur as additional unwanted FPGA inputs,
the actual names of the additional signals have to be taken from the Compilation report (Fitter
–
Resource Section – Input Pins).
1. Locate the COMPONENT declaration of the EtherCAT_IPCore (COMPONENT), and add the
additional input signals in the PORT section declaration:
COMPONENT EtherCAT_IPCore
GENERIC (
PRODUCT_ID0 : STD_LOGIC_VECTOR := X"1234";
PRODUCT_ID1 : STD_LOGIC_VECTOR := X"5678";
[...]
USERSET2 : STD_LOGIC_VECTOR := X"0000";
USERSET3 : STD_LOGIC_VECTOR := X"0000";
PDI_GPIO_WIDTH : NATURAL
);
PORT (
SIM_FAST : IN STD_LOGIC;
PHY_OFFSET : IN STD_LOGIC;
nRESET : IN STD_LOGIC;
CLK25 : IN STD_LOGIC;
[...]