BECKHOFF ET1100 - Manual (Page 29)

EtherCAT IP Core for Altera FPGAs
Slave Controller – Application Note FAQ 25
2. Locate the instantiation of the EtherCAT_IPCore (PORT MAP ), and set the additional inputs to ‘0’:
EtherCAT_IPCore_inst : EtherCAT_IPCore
GENERIC MAP (
PRODUCT_ID0 => X"1234",
PRODUCT_ID1 => X"5678",
[...]
USERSET2 => X"0000",
USERSET3 => X"0000",
PDI_GPIO_WIDTH => 0
)
PORT MAP (
SIM_FAST => '0',
PHY_OFFSET => '0',
nRESET => nRESET,
CLK25 => CLK25,
[...]
3. Save the changes and start Compilation in Quartus. Check the Fitter reports: no additional signals
with path information and locations assigned by the fitter should be left.
You have to repeat these steps each time you generate the EtherCAT IP Core again, because this will
overwrite the changes.